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Verilog

Getting Started​

  • FPGA Workflow - Complete FPGA development process from project creation to bitstream generation
  • Timing Constraints - Circuit timing theory including setup/hold times and clock skew

Core Concepts​

  • Module - Module structure, ports, instantiation, functions, and tasks
  • Data Types - Constants, vectors, arrays, numbers, registers, nets, and preprocessor directives

Modeling Styles​

  • Gate - Primitive gates, gate instantiation, and generate statements
  • Dataflow - Continuous assignments and operators
  • Behavior - Procedural blocks, control structures, and delay specifications

Advanced Topics​

  • State Machine - Finite state machines and arithmetic state machines
  • SystemVerilog - SystemVerilog enhancements including enums, structs, interfaces, and OOP

Platform​

  • Xilinx U280 - Xilinx U280 FPGA board specific toolchain and host application
  • AXI Protocol - AXI bus protocol channels and burst transfers

Components​

  • Hardware Components - Hardware component implementations including multipliers, ALU, memory, etc.

Best Practices​

  • Best Practices - Coding guidelines, synthesizable constructs, and parameter usage